By Tim Newark
Книга описывает завоевательские войныот эпохи фараонов и вплоть до 19-го столетия
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That provide tolerance to defects or device failures. At the architectural level, defect and fault tolerance is achieved through techniques of assembling collections of these nano-scale devices. Finally, defect and fault tolerance at the application level involves features of the computing applications themselves that allow them to operate correctly despite defects and faults in the computing system on which they execute. Though nano-scale devices have some features that 42 NANO, QUANTUM AND MOLECULAR COMPUTING may make them tolerant to some defects and faults and though some applications themselves may have some inherent defect or fault tolerance, most of the techniques being investigated relate to the architectural level.
80:3817–3819, 2002. [60] N. Yang, W. Henson, and J. Hauser. Modelling study of ultrathin gate oxides using tunneling current and capacitance-voltage measurement in mos devices. IEEE Trans On Elec Dev, 46(7), july 1999. [61] Z. Yao, C. L. Kane, and C. Dekker. High-field electrical transport in single-wall carbon nanotubes. Phys. Rev. , 84:2941–2494, 2000. This page intentionally left blank II DEFECT TOLERANT NANO-COMPUTING This page intentionally left blank Preface In his famous book from 1956, "Probabilistic Logics and the Synthesis of Reliable Organisms from Unreliable Components", John von Neumann had talked about building reliable computing systems from fault-prone components.
Lundstrom, and S. Datta. Metal-insulatorsemiconductor electrostatics of carbon nanotubes. Appl. Phys. , 81:1486, 2002. [27] J. Guo, M. Lundstrom, and S. Datta. Performance projections for ballistic carbon nanotube field-effect transistors. Appl. Phys. , 80:3192, 2002. [28] S. Guo, S. Datta, and M. Lundstrom. A numerical study of scaling issues for schottky barrier carbon nanotube transistors. IEEE Transactions on Electron Devices, 51:172, February 2004. [29] F. Hamzaoglu and M. Stan. Circuit-level techniques to control gate leakage for sub-100 nm cmos.
