By Ian O’Connor, Junchen Liu, Jabeur Kotb (auth.), Jürgen Becker, Marcelo Johann, Ricardo Reis (eds.)
This booklet comprises prolonged and revised types of the easiest papers awarded on the seventeenth IFIP WG 10.5/IEEE overseas convention on Very huge Scale Integration, VLSI-SoC 2009, held in Florianópolis, Brazil, in October 2009. The eight papers incorporated within the ebook including keynote talks have been rigorously reviewed and chosen from 27 papers offered on the convention. The papers conceal a wide selection of excellence in VLSI expertise and complex examine addressing the present pattern towards expanding chip integration and know-how strategy developments bringing approximately stimulating new demanding situations either on the actual and system-design degrees, in addition to within the attempt of theses systems.
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Extra resources for VLSI-SoC: Technologies for Systems Integration: 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianópolis, Brazil, October 12-14, 2009, Revised Selected Papers
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With gains on the order of 10X - 100X in integration density, at a lower cost than planar-only downscaling and integration. Challenges and Emerging Technologies for System Integration 25 Fig. 1. Conceptual hierarchy of alternative computing devices (ITRS, 2007) The ITRS industry panel assesses continuously the emerging devices, which are candidates to replace silicon. Figure 1 from ITRS conceptually separates the emerging devices in terms of the state variables used to enable in the physical world the digital state abstraction (charge, as in CMOS devices, phase state of a molecule or atom, and spin or magnetic number state of a given electron level or molecule, respectively).
EEE DL talk at Federal University of Rio Grande do Sul, mimeo, p. : Design Automation of Transistor Networks, a New Challenge. In: IEEE International Symposium on Circuits and Systems, ISCAS 2011, Rio de Janeiro, Brazil, May 15-19, pp. 2485–2488. : Technology Mapping in MIS. In: IEEE ICCAD, pp. : Transistor Level Automatic Layout Generator for nonComplementary CMOS Cells. In: International Conference on Very Large Scale Integration, IFIP/CEDA VLSI-SoC 2007, pp. 116–121 (2007) Thermal Modeling and Management of Liquid-Cooled 3D Stacked Architectures Ay¸se Kıvılcım Co¸skun1 , Jos´e L.
For example [11, 12] provide insights into using on-chip temperature sensors in processors that contain integrated sensors, such as IBM POWER series processors. However, many of the hot spots can be missed as the number of sensors is limited. Another runtime thermal characterization method is IR thermal imaging [13, 14]. While this technique can capture the detailed thermal map in real-time, the limited sampling rate of the IR camera may filter out high-frequency transient thermal fluctuations. Dynamic thermal management in response to thermal measurements in microprocessors has been first introduced by Brooks et al.
